In current high-speed and high-precision ADC (Analog-to-Digital Converter) circuits, the sample and hold switch circuit is a bottleneck for the converter design, and sampling Field Effect Transistors are an integral part of the sampling circuit, so the overall performance of the sample and hold switch circuit is largely depended on the speed and precision of the sampling Field Effect Transistor. In a condition of deep submicron technology, a gate voltage bootstrap frame is connected to the sampling Field Effect Transistor which is connected with an input signal so as to reduce on-resistance and nonlinearity of the sampling Field Effect Transistor and expand the input signal range. However, the linearity of the traditional sampling Field Effect Transistor declines with the increase of the sampling frequency, which restricts dynamic range of the sample and hold switch circuit, thereby it's hard to meet the demands of the dynamic performance of the sampling signal required by the high-speed and high-precision ADC.
Therefore, it is necessary to provide an improved sample and hold switch circuit to overcome the above drawbacks.